In recent years, there is a tendency that the storage products employing a flash memory prevails over the market, in accordance with which there is higher demand on the larger capacity and higher performance of such products. In order to enlarge the capacity of such products, it is important to improve on the packaging density of such various devices as chips, LSIs, ASICs and CPUs on the substrate.
For instance, if a memory controller can be made smaller in size, it allows the packaging density of the devices on the substrate to be enhanced. Such a silicon chip as a memory controller is sealed in a package of a predetermined size. In order to make the memory controller smaller in size, it is effective to reduce the number of its signal lines, because the physical size of such a package depends on the number of pins.
In Patent Literature 1, a technique to secure the memory bandwidth as required while restraining the number of signal lines and pins on the chips and the like from increasing is disclosed. At the abstract of Patent Literature 1, there is disclosure saying ‘as regards a plurality of memories, a data bus is connected to the respective memories independently from one another. Further, as regards a plurality of memories, a selection signal line is connected to the respective memories independently from one another. A command signal line is connected to the plurality of memories with the same shared among them. A control unit, when an access request for at least two memories among the plurality of memories is outputted from a bus master, performs command control such that the overlapped command corresponding to such access request is not issued at the command signal line’. This technique permits the number of signal lines and pins on chips to reduce and the devices to be made smaller in size and the high density packaging of the storage products to be realized.